The IDLC device comprises synchronous and asynchronous sections, interfacing respectively to communication ports and the mentioned system bus. The DMAC and MIO units mentioned above are in the asynchronous section. Intended for primary rate ISDN applications, the IDLC was designed to provide service to a large number of communication channels (as many as 32 channels full duplex, each operating at a rate of 64 kbps-64,000 bits per second-in each direction of communication).
A problem giving rise to the present invention was detected during design of a VLSI device related to the IDLC as a functional and logical subset of the latter. This device, termed the Integrated ISDN Module (or IIM), was designed principally for basic rate ISDN applications with capability of serving on the order of 6 full duplex basic rate channels (64 kbps in each communication direction). The intent was for the IIM to be used as a component of a communication card, and provide master bus control and DMA control relative to a number of different external system buses; including buses operating in accordance with the IBM Micro Channel.sup.1 architecture. FNT .sup.1 IBM and Micro Channel are trademarks of the International Business Machines Corporation.
The problem was detected in considering a prototype design for the IIM based on usage of DMAC and MIO units corresponding directly to those in the IDLC (but configured to serve 6 full duplex communication channels instead of 32 channels). Investigation reveals that this configuration could operate marginally under worst case assumptions regarding Micro Channel bus loading and channel activity in the device. Under worst case bus load circumstances (maximum number of devices connected to the bus and all assumed to be arbitrating for the bus at maximum rates), the IIM would have access to the bus only at intervals of about 200 microseconds (from the time it begins arbitrating for access) and would be allowed to retain access to the bus for only 7.8 microseconds each time that it gained access.
Worst case channel activity assumptions envision all 12 channels in the IIM device (6 receive channels and 6 transmit channels) requesting data word (32 bits) transfers from DMAC simultaneously. This condition occurs when data word storage spaces in the device local memory (FIFO RAM) allocated to all receive channels are simultaneously full and data word storage spaces allocated to all transmit channels are simultaneously empty. Under these conditions, and considering other latency factors due to pipelining in the device synchronous section (effectively providing buffer storage of up to 4 more bytes of data per channel), the DMAC and MIO would have 500 microseconds of additional time to transfer 12 data words relative to FIFO RAM before incurring overrun errors in one or more receive channels or underrun errors in one or more transmit channels.
The 500 microsecond limitation can be understood by considering that if all 12 channels were actively operating at the contemplated maximum rate of 64 kbps (64000 bits per second), each receive channel would receive a byte on the average every 125 microseconds, and transmit channel would transmit a byte every 125 microsecond. Thus, each receive/transmit channel would receive/send 4 bytes (the buffer capacity available to it in the synchronous section pipeline) every 500 microseconds. Thus, from the time a receive/transmit channel fills/empties its respective buffer in FIFO RAM, DMAC/MIO have only 500 microseconds to transfer respective receive data between FIFO RAM and host memory before error is charged. Accordingly, if all 12 buffers in FIFO RAM are simultaneously ready for transfers, DMAC/MIO have only 500 microseconds to carry out 12 respective word transfers between FIFO RAM and host memory. Now if the foregoing 12 transfers are to be made over a maximally loaded Micro Channel system bus, DMAC/MIO would have access to the bus for only 15.6 microseconds in any 500 microsecond interval (based on worst case access of 7.8 microseconds every 200 microseconds, and noting that 500 microseconds would encompass only two 7.8 microsecond accesses).
However, DMAC and MIO as designed for the IDLC are tightly time-interlocked units, requiring approximately 2.2 microseconds to carry out a word transfer (about 1.2 microseconds for DMAC to prepare needed instruction information and about 1.0 microseconds for MIO to control the associated data transfer at the bus). Thus, in 7.8 microseconds at most 4 word transfers could be completed (assuming that the 1.2 microseconds of preparation for the first transfer is carried out before MIO holds the bus, so that a first word could be transferred in the first 1 microsecond of access, and assuming that three more words could be transferred in the remaining 6.6 microseconds).
The original DMAC and MIO designs did not allow overlapping in time of preparational functions relative to one channel with the data transfer functions of another channel because of the available registers in the DMAC, their usage in the preparation and data transfer processes and time interdependencies between the DMAC and MIO relative to such usage.
Time constraints of the worst case scenario envisioned above--need to carry out 12 data word transfers on a maximally loaded Micro Channel bus relative to 12 simultaneously "ready" channels in 400 microseconds--become more severe when special functions such as command chaining are required. The IDLC was designed to provide command chaining service relative to transmit channels. In such operations 3 words of DCB (Device Control Block) information, representing commands chained to previously executed commands, must be fetched from host memory to local device memories (FIFO RAM and DMAC RAM). If the DCB fetches are not handled quickly, after exhaustion of the previous command is detected, in order to maintain continuity of operation in respective transmit channels (i.e. avoid underruns). Thus, if need for one or more command chain DCB fetches arises when the 12 channels are "ready", the DMAC and MIO would have to handle 15 or more word transfers in a 500 microsecond interval. However, taking into account the probability of having command chaining requirements coincide with ready conditions in all channels, and the probability of a bus being maximally loaded (so that arbitration contention is virtually continuous, which is the condition under which each device holding the bus is limited to 7.8 microseconds of use), it was determined that a reasonably "safe" design target for the IIM would be to accommodate handling of 12 ready channels in any 400 microsecond period of Micro Channel bus operation.